AP7002 THREE DIMENSIONAL NETWORKS ON CHIP - ANNA UNIV PG 1ST SEM SYLLABUS
| ANNA UNIVERSITY, CHENNAI REGULATIONS - 2013 M.E. APPLIED ELECTRONICS AP7002 THREE DIMENSIONAL NETWORKS ON CHIP COURSE OBJECTIVES: To introduce the concept of 3D NOC. To study the architectures and protocols of 3D NOC. To identify the types of fault and study the testing methods for fault rectification. To learn DimDE router for 3D NOC. UNIT I INTRODUCTION TO THREE DIMENSIONAL NOC Three-Dimensional Networks-on-Chips Architectures. – Resource Allocation for QoSOn-Chip Communication – Networks-on-Chip Protocols-On-Chip Processor Traffic Modeling for Networks-on-Chip UNIT II TEST AND FAULT TOLERANCE OF NOC Design-Security in Networks-on-Chips-Formal Verification of Communications in Networks-on- Chips-Test and Fault Tolerance for Networks-on-Chip Infrastructures-Monitoring Services for Networks-on-Chips. UNIT III ENERGY AND POWER ISSUES OF NOC Energy and Power Issues in Networks-on-Chips-The CHAIN works Tool Suite: AComplete Industrial Design Flow for Networks-on-Chips UNIT IV MICRO-ARCHITECTURE OF NOC ROUTER Baseline NoC Architecture – MICRO-Architecture Exploration ViChaR: A Dynamic Virtual Channel Regulator for NoC Routers- RoCo: The Row-Column Decoupled Router – A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks. Exploring Fault Tolerant Networks-on-Chip Architectures. UNIT V DIMDE ROUTER FOR 3D NOC A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3D Architectures- Digest of Additional NoC MACRO-Architectural Research. TOTAL: 45 PERIODS REFERENCES: 1. Chrysostomos Nicopoulos, Vijaykrishnan Narayanan, Chita R.Das" Networks-on - Chip " Architectures A Holistic Design Exploration", Springer. 2. Fayezgebali, Haythamelmiligi, Hqhahed Watheq E1-Kharashi "Networks-on-Chips theory and practice CRC press. |
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